1. Field of the Invention
This invention relates to lithographic processes for creating very high spatial resolution structures at the nanometer scale. In particular it relates to the use of voltage based probes that are positioned using hard disk drive technology.
2. Description of the Related Art
Nanolithography using high resolution imaging systems like the scanning probe microscope (SPM) and atomic force microscope (AFM) surged in the years between 1990 and 2001 following its application to the nano-patterning of a silicon surface in 1990 by Dagata et al. (J. A. Dagata et al., “Modification of hydrogen-passivated silicon by a scanning tunneling microscope operating in air,” Appl. Phys. Lett., vol 56, pp. 2001, (1990)) This technique uses a high voltage (>1 V) biased scanning tip with a tip size of tens of nanometers and scans over a hydrogen passivated silicon surface. The silicon substrate is grounded to form a potential difference between the tip and the substrate surface over a tip-to-surface distance of several nanometers. Due to the close proximity between the STM tip and the surface, an electric field >1 V/nm is easily achieved and electron emission from the tip to the surface occurs with a current in the nA (nanoampere) scale. This electron current emitted from the tip leads to an assisted oxidation of the hydrogen-passivated silicon surface area that the tip scans across and consequently creates an oxidized line of nanometer scale on the silicon surface during the scan. By using a subsequent liquid chemical etching process, particularly for a Si (100) surface, the etching rate is different between the oxidized/anodized portion of the silicon surface and the non-modified portion. This oxidized nano-pattern can be used as a nano-lithography mask (see E. S. Snow, et al., “Fabrication of silicon nanostructures with a scanning tunneling microscope,” Appl. Phys. Lett., vol. 63, pp 749, (1993)). This was the first proof of the viability of electric field assisted oxidation for nanolithography purposes. Subsequent work extended the technique to include STM, SPM and AFM in non-contact and contact modes to achieve nanolithography and nano-patterning on various metallic, semiconductor and even polymeric and organic surfaces.
Referring to FIG. 1, there is shown, schematically, a diagram of a generic, prior art voltage biased, probe-based nanolithographic system that could operate using SPM, STM, or AFM systems. In the diagram (10) is a voltage source used to bias the probe (40). An appropriate current meter (20) registers the electron flow from the probe to the target layer (50). The target layer is attached to a suitable grounded substrate (60). Although most prior work, as shown in the figure, utilized a method involving substrate grounding and probe tip electron emission, i.e., a negative voltage bias on the probe tip, positive biasing has also been tried to produce lift-off of Au—Pd nano-patterns after exposure of a thin polymethylmethacrylate (PMMA) photoresist (see, M. A. McCord and R. F. W. Pease, “Lift-off metallization using poly(methyl methacrylate) exposed with a scanning tunneling microscope,” J. Vac. Sci. Technol. B, vol. 6, pp 293, (1998)). The positive bias scheme is expected to draw electrons from the substrate, producing less inelastic scattering and thereby producing sharper features in the PMMA, especially at high bias voltages.
For most of the published work a spatial resolution of the order of between 10 and 20 nm was consistently achieved. This resolution is superior to that obtained by conventional optical lithography and also superior to state-of-the-art high energy electron beam (e-beam) lithography, which produces resolutions in the order of 30 nm. In addition, as compared to advanced e-beam lithography systems which are performed under extreme vacuum and temperature conditions, this method can be performed in air without extremes in temperature and is, therefore much more economical and easier to perform. This probe-tip electron emission lithography utilizes low energy electrons during the resist exposure, which theoretically produces high spatial resolution without the backscattering that accompanies high energy electrons. In addition, the voltage biased probe assisted oxidation can be used to produce a lithography mask directly without any auxiliary photoresist processes and, similarly, can produce direct patterning of a target semiconductor or metallic film, which is surely a promising and advantageous aspect of the method.
Among the prior efforts to utilize SPM for nanolithography, there are modifications and variations that include both oxidation and photoresist exposure, material deposition and material removal. For lithography purposes, the use of photoresist is the most investigated method and two approaches have been studied. The first approach is to use the SPM tip-emitted electron current to expose thin layer photoresists, which include the popular PMMA (cited above) and other organic materials. The cited publication of McCord and, in addition, the publication of A. Majumdar et al. (“Nanometer-scale lithography using the atomic force microscope,” Appl. Phys. Lett., vol 61, pp 2293 (1992)) and the work of S. W. Park et al. (“Nanometer scale lithography at high scanning speeds with the atomic force microscope using spin on glass” Appl. Phys. Lett., vol. 67, pp 2415 (1995)) show examples that can be achieved by such lithography.
In the second approach, also well documented in publications, the electric field induces localized oxidation/anodization of the path scanned by the probe tip across the target surface. The target material in this case can be crystalline or amorphous silicon and many different kinds of metals including, but not limited to Ti, Ta and Cr.
Even though the various experiments in SPM based lithography have produced results that are superior to all existing lithography techniques, the technique has not been implemented in any commercially available systems. The major reason for this lack of commercialization is the fact that the SPM, STM and AFM methodologies are intrinsically low throughput systems. To use the technique for commercially viable wafer level lithography, the positioning system has to be capable of nanometer position resolution over travel distances on the order of several inches, all the while maintaining a nanometer tip-to-target clearance (contact mode being unacceptable due to tip wearing) over the entire distance with a speed that needs to be several times faster than the reported microns per second in the SPM, STM, and AFM published results cited above. Such stringent requirements are beyond the capabilities of the reported piezo and linear stage based SPM, STM and AFM systems. Although efforts and proposals have been made to address this low throughput issue using 2-dimensional probe arrays, the complexity and cost of such a scheme make it unfavorable when compared to more straightforward methods such as high energy e-beam lithography and deep-UV photolithography.